1. Field of the Invention
This invention relates in general to the fabrication of semiconductor integrated circuits (ICs) and, in particular, to the fabrication of dynamic random-access memory (DRAM) IC devices. More particularly, this invention relates to the fabrication of the bottom electrode for the storage capacitor for DRAM IC devices.
2. Description of Related Art
DRAM devices rely substantially on the storage capacitor of the memory cell units for data storage. Inherent leakage characteristics of these storage capacitors requires that the capacitance be sufficiently large to sustain reasonable data retention time. Insufficient data retention time implies that the DRAM memory cells be refreshed at an excessively large duty cycle, which degrades the overall performance. However, as ULSI DRAM devices are being fabricated, utilizing more and more refined resolutions, die area assigned to each memory cell unit in the DRAM device has been decreasing. This directly reduces the available surface area that is allowed within the already limited spaces. Efforts have been devoted to increase the electrode surface area for these storage capacitors. Among the efforts, hemispherical-grain polysilicon (HSG-Si) layers have been formed over the surface of the capacitor bottom electrode in order to increase the effective electrode surface area.
FIGS. 1A-1D depict a conventional process for fabricating a bottom electrode for DRAM memory cell storage capacitors in a series of selected process stages. As is illustrated in FIG. 1A, field oxide layers 12 are first formed over the surface of the device substrate 10 used to fabricate cell units of the DRAM device. Surface of the substrate 10 is then covered with a layer of dielectric 14 having contact openings 16 formed therein. These openings 16 reveal the surface of the source/drain regions of the cell unit transistors embedded in the substrate; these are not detailed in the drawing.
Then, as is illustrated in FIG. 1B, an electrically conductive material is then deposited over the surface of the device substrate, covering the surface of the dielectric layer 14, and filling into the openings 16 formed therein. This deposited conductive layer of material is then patterned to form the conductor layer 18, as shown in the cross-sectional view. The material used to form the conductive layer 18 can be, for example, doped polysilicon formed, for example, in a low-pressure chemical vapor deposition (LPCVD) procedure.
With reference to FIG. 1C, it can be observed that an HSG-Si layer 20 is then formed over the surface of the entire substrate structure at this stage. This includes covering the surface of the conductive layer 18 and the surface of the dielectric layer 14 not covered by the conductive layer 18. To achieve this, the HSG-Si layer 20 may be formed, for example, in an LPCVD procedure utilizing SiH.sub.4 or Si.sub.2 H.sub.6 supplied by the reaction gaseous source. The deposition temperature is controlled to be in the range between the formation temperature for amorphous silicon and polysilicon. The HSG-Si layer 20 is formed directly by deposition.
Then, in FIG. 1D, an anisotropic etching procedure is performed to etch back the HSG-Si layer 20, so that the portions of the HSG-Si layer 20 covering the dielectric layer 14 can be removed. This prevents the undesirable short-circuiting between the consecutive capacitor electrodes formed on the device substrate. The deposited HSG-Si layer 20 is integrated with the conductive layer 18 to form the bottom electrode for the DRAM memory cell storage capacitor.
Such prior-art fabrication procedures employing direct etching against the HSG-Si layer 20, though capable of removal of the HSG-Si layer formed over the surface of the dielectric layer 14, also damage the HSG-Si layer 20 itself. In particular, the portion of the HSG-Si layer 20 covering the conductive layer 18 is most vulnerable to the etching. On excessive occasions, the HSG-Si layer 20 and the conductive layer 18 embedded beneath are damaged to a level that current leakage occurs through the dielectric layer 14. Thus, the etching procedure has to be controlled to avoid excessive damages to the HSG-Si layer.
Further, if the etching-back procedure is not properly controlled, micro-bridging phenomena will arise between bottom electrodes for the cell units. As a result, the capacitor structure for the cell units may eventually be damaged.